1. Field of the Invention
The present invention relates to a semiconductor device, a design apparatus, and a program, and more particularly to a semiconductor device which includes ring-gate MOS transistors, and a design apparatus and a program for designing the semiconductor device.
2. Description of Related Art
When manufacturing semiconductor devices such as a dynamic random access memory (DRAM), chemical mechanical polishing (CMP) process is used for planarization processing. The CMP process is characterized by feeding of slurry that contains various chemical components while mechanically polishing the object to be polished. The chemical components modify the surface for effects such as improved processing rate and a reduction of fine scratches on the surface.
CMP process is also used for planarizing the surface of an insulating film deposited on a wiring pattern. When using the CMP process for such applications, so-called dishing phenomenon can occur if the wiring pattern under the insulating film has a wide open area. The dishing phenomenon refers to the formation of a dish-like recess in that part of the insulating film. To avoid occurring of the dishing phenomenon, it is effective to form a dummy pattern around the wiring pattern so as to reduce the open area. Japanese Patent Application Laid-Open Publication No. H09-107028 discloses an example of the dummy pattern.
The inventor of the present invention has studied the use of metal oxide semiconductor (MOS) transistors having a ring-shaped gate electrode (ring-gate MOS transistors) for a semiconductor device with the purpose of obtaining large gate widths.
A ring-gate MOS transistor can be fabricated generally by the following manufacturing steps. Initially, a gate insulating film and a gate electrode are formed on a semiconductor substrate, followed by patterning into a ring shape. Next, an insulating film (sidewalls and a gate cap) is formed on the sides and top of the gate electrode. Impurities for forming impurity diffusion regions are implanted into the semiconductor substrate inside and outside the ring. Typically, the inside of the ring is a drain region, and the outside a source region. The resultant is covered all over with an interlayer insulating film, and polished by the CMP process until the gate cap is exposed. Subsequently, necessary contact holes are formed in the interlayer insulating film and the gate cap, and contact conductors for connecting the gate electrode, drain, and source to upper wiring are formed therein.
When used for a semiconductor device, a large number of ring-gate MOS transistors are arranged on a single semiconductor substrate. Inevitably, a number of ring-gate MOS transistors are simultaneously formed in a single step. The ring-gate MOS transistors are not always arranged in a closely packed configuration, and the foregoing open area can thus occur between the ring-gate MOS transistors. Since such open areas may cause the foregoing dishing in the CMP step, a dummy pattern is formed in the areas between the ring-gate MOS transistors, if needed, when patterning the gate electrodes.
Some circuits need ring-gate MOS transistors that have an extremely large ring diameter. Having a large area inside the ring, such ring-gate MOS transistors can sometimes cause dishing inside their ring in the CMP step during manufacturing.
As a concrete example, the first input stage circuits and temperature sensing circuit of a DRAM need to use ring-gate MOS transistors of large gate lengths in order to reduce PVT (Process, Voltage, and Temperature) effects. The larger the gate length, the lower the current supply capability becomes accordingly. To compensate the drop, the gate width needs to be made even greater. That is, the ring diameter becomes extremely large.
As described above, dishing phenomenon can occur not only in the areas between ring-gate MOS transistors but also in the areas inside the rings. Developing a technology for suppressing the occurrence of dishing phenomenon has thus been needed.